I thought I'd do an example of a common use for a control loop system, so this
will be a look at phase locked loop frequency synthesizers. A PLL is a
feedback loop system that generates multiple frequencies (it could be audio to
RF) by tuning a variable oscillator that’s compared to a crystal
reference. In virtually all communications systems designed since the
70s, somewhere in the system you'll find frequency synthesis by phase locked
loop.
A phase locked loop is a control system; a negative feedback loop that
compares the phase of two signals and generates an error that's used to
correct the difference between them. Since all negative feedback systems are
continually correcting themselves, you can think of it as a limited
"self-correcting" system. Here's a diagram of a simple PLL:
The variable signal is generated by a Voltage Controlled Oscillator (VCO), and
divided down in frequency. This divider is programmable to divide by a range
of integers. The divided signal’s phase is compared to the reference, (which
is also usually divided down from a higher frequency) and an error signal is
generated. The comparison is most often performed in a Phase/Frequency
Detector (PFD) which (as its name implies) is sensitive to frequency
differences as well as phase differences. When the two inputs are very far
apart in frequency, it generates a beat note at its output. This helps the
system find its place and lock up faster than other types of detectors. There
are other, simpler phase detectors that have pretty much fallen out of use
except for specialized applications: double-balanced mixers, and exclusive-OR
gates are the most common of these. The output of the PFD is usually sent
through an Op Amp integrator and lowpass filtered before being applied to the
oscillator's control port. The loop filter doesn’t have to be an active
filter, but tends to be one in high performance PLLs. Many cellular phones,
WLANs and other "cheap wireless" designs use passive RC (Resistor-Capacitor)
filters. The main reason to use an opamp active filter is to allow larger VCO
control voltage swings than the PLL chip will allow. This, in turn, helps
minimize VCO noise.
When I first started working on RF synthesizers, the reference dividers were a
handful of chips, perhaps five, the programmable dividers were another four or
five, and the PFD was still another chip. With current parts, you can get
everything for a PLL, including the VCO in a single surface mount technology
(SMT = tiny) chip.
PLLs can be designed to generate any frequency, from audio to millimeter
waves, and they can be very simple (like this example) or very complex.
But just because you can build one doesn’t mean it will be worth the effort.
When industry first started building synthesizers, a flood of really rotten
radios hit the ham market. Before synthesizers became widespread, you chose
the frequency you were tuned to either by multiplying crystals (in VHF/UHF
gear), by mixing crystals and Variable Frequency Oscillators, or, in the
cheapest receivers, by a free-running VFO alone. It’s much easier to build a
really crappy synthesizer than it is to ruin a crystal. To understand what
separates a good one from a bad one requires some understanding of how loops
generate and shape noise. Those discussions can be rather involved, so I won’t
get into those. You simply can’t design a synthesizer without knowing your
requirements for noise, spurs, and modulation.
Most of the critical concepts, behaviors and parameters of a PLL can be
covered with a simple example based on some easy numbers. Let's assume that
the loop is generating 800 MHz, with a reference frequency of 100 kHz. That
means the divider is set to 800/0.1 or 8000. What happens if the counter is
suddenly incremented to divide by 8001? The frequency at the input of the PFD
is now lower than the reference: it's (briefly) 800/8001 or 99.9875 kHz. When
the edges of divided VCO and the reference at the PFD input no longer line up,
this causes an asymmetry in the pulses going to the loop filter. The loop
filter integrates the difference, causing the voltage applied to the VCO (and
VCO output frequency) to go up until the edges occur at the same time. That
can only happen when the VCO is running at 800.1 MHz.
Another way of looking at this is that the system is acting as a frequency
multiplier. We can multiply the 100 kHz reference by any number that we enter
into the dividers; and in a typical synthesizer like this, the output
frequency has to be an integer multiple of the reference. Octave tuning ranges
(2:1), or wider, are routine. This is a frequency multiplier that multiplies
by 8000. Typical circuits you can find will multiply by maybe up to four
times. The amount of hardware it takes to generate a range of
frequencies on 100 kHz spacing is much higher without the PLL.
Since we've effectively multiplied a crystal, the benefit of the PLL is that
we've transferred the crystal's characteristics onto the free-running
oscillator. It's now as stable and accurate as the crystal. But there's a
cost. Like any multiplier, spurious outputs and noise are made worse by the
multiplication ratio; in fact, they're 20 log N worse. That means noise on the
crystal oscillator is made worse by 78 dB in this example. Crystals are so
good, though, that they can usually withstand that sort of degradation. I'd be
delighted if that were the only noise source.
A characteristic if this sort of simple PLL is that it can only step in
frequency differences that are the input to the phase detector. For a simple
example, you might want to step in 5 kHz steps for the 2 meter FM band. That
means that the frequency at the phase detector from both the reference and the
VCO have to be divided down to 5 kHz. You can divide them further, say to 1
kHz for frequency steps that small, and that causes an increase in the noise
floor out of the synthesizer, which can create in-channel noise from nearby,
off-channel signals.
There are limits to this because every time you increase the division you
increase the noise (did I ever mention physics is a bitch?). The increase in
noise is 20*Log(division ratio). That means if I want to make my synthesizer
tune in 1 kHz steps, I have divide by a factor of five more, and 20*log(5) is
14 dB. By the time you get to an HF radio that may be tuning with a tuning
step of 10 Hz, the noise in a simple design like this is unbearable and other
techniques are needed.
What other techniques? One is called Fractional-N Synthesis. Imagine the frequency
synthesizer that we just played with has a wire coming out that allows us to
toggle the least significant bit of the counter. If we set the signal on that wire high, it divides
by 8001 giving us 800.1 MHz, and if we set it low, it divides by 8000 giving
us 800.0. What would happen if we hooked this bit up to a square wave
generator and toggled it?
If we toggled it slowly, the synthesizer would hop back and forth between
N=8000 and (N+1) = 8001 (800 and 800.1 MHz). If it's slow enough, you can watch hop back and forth on a spectrum analyzer. If we increased the toggle rate
to something higher, the output
changes. Now we achieve an average divider ratio of (N+(N+1))/2 or N+1/2 and the output shows up at 800.050 MHz.
This is the basis of all fractional N techniques, and you can actually build a
PLL that will work this way using 1980s technology: an off the shelf parallel
entry PLL chip (e.g., MC145152) and latches (SN7475) that toggle the
programming bits between N and N+1. You'll need something to generate the square wave toggle, like a "good ole triple nickel" 555 timer chip.
The advantage of doing this Fractional-N is that you've just decreased your step size,
giving you the same results as dividing your reference by another factor of
two, but you have cheated the universe out of the 6 dB noise hit you would get
by using the lower reference! But this is engineering; there has to be a cost,
and there is. You will get different spurious outputs at the fractional
offset, the effective new reference. (That is, the old system would tend to
produce spurs at 100 kHz either side of the carrier; this will tend to produce
them at 50 kHz spacing). Modern chips are available that allow a step size of
1/16 the reference: that's a noise improvement of 24 dB. And that's not the
end of it.
Phase Locked Loops are a specialty of their own in radio design,
although the advent of band-sampling radios based on really fast Analog to
Digital Converters are pushing PLL design. The entire field is always
changing, and there are always new tricks to learn. That's part of the
fun. I thought that in light of
my talking about feedback and control loops, I'd do a piece on how they really get used. This is just one small
example.
